In the art of semiconductor integrated circuit memory device planar manufacturing, it is known to fabricate individual memory cell resistors using polycrystalline silicon ("poly") of an appropriate doping. This is true for static random access memory ("SRAM") devices. SRAMs allow for both data storage (i.e., writing) and data retrieval (i.e., reading) of its memory cells in random order independent of the physical locations of the cells. In a particular SRAM design having two load resistors in a single SRAM cell, both resistors typically comprise doped poly. The layer of poly in which the resistors are formed usually comprises a second layer of poly; a first layer of poly being used to form, inter alia, the gates of the four transistors in a typical SRAM cell. See Wolf, S., "Silicon Processing For The VLSI Era, Vol II, Process Integration" 1990 pp 567-583.
In U.S. Pat. No. 5,141,597 to Adams et al. and assigned to same assignee as that of the present invention, there is described a process of forming thin polysilicon resistors preferably in the first level of poly (i.e., in the same level of poly as the transistor gates). However, the invention in Adams et al. may be applied to a second level of poly, if desired. (Column 2, lines 3-10). The invention in Adams et al. relates to a method of forming poly resistors in which the resistor area is defined and initially etched down to an appropriate thickness less than the thickness of the poly interconnect regions. Both the resistor and interconnect regions are doped and defined by patterning and etching steps.
Adams et al. allude to the fact that subsequent steps are needed to form the poly resistors beyond those described and claimed in detail therein. (Column 2, lines 41-46). It was discovered that during such a subsequent step (i.e., of further resistor patterning and etching), a portion of the poly resistor region was undesirably removed. This had a profound effect on the resistor value. The result was a very poor resistor manufacturing yield to specification.
Specifically, a spacer oxide comprising, e.g., silicon oxide, was formed over the entire single layer of poly, including the poly resistor region. The spacer oxide was then etched to clear all of the oxide off the poly. This was done by setting an etch endpoint, and then overetching to account for non-uniformities. During this process, the selectivity to the poly became very critical in reference to control of the poly resistor thickness. It was found that the etch endpoint and selectivity were not adequate to control the resistor values. Thus, it was difficult to yield SRAMs having resistor values within specification.
The specification is strict due to the fact that poly resistors have a high temperature coefficient. This results in a wide range of the timing of the write pulse to the SRAM cell when operating over the entire military temperature range. Since SRAMs must be designed to operate with this wide range in pulse width and wide range in resistivity, it is critical that an accurate resistance value be provided for the SRAM load resistors.